verilog HDLBits刷题[Verification:Writing Testbenches]“Tb/and”---AND gate

1、题目2、分析题目提供与门模块需要写对应的testbench模块3、代码module top_module(); reg [1:0]in; wire out; initial begin in2b00; #10 in2b01; #10 in2b10; #10 in2b11; end andgate andgate_inst(.in(in),.out(out)); endmodule4、结果